1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming transistors with air gaps arranged laterally adjacent the gate conductors to reduce capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are then patterned to form a gate conductor with junction regions within the substrate adjacent to and on opposite sides of the gate conductor. The gate conductor and junction regions are then implanted with a light concentration of impurity dopant species to form lightly doped drain ("LDD") regions self-aligned to the gate conductor sidewall surfaces. Following the LDD implant, sidewall spacers composed of, e.g., silicon dioxide or silicon nitride are formed laterally adjacent to the opposed sidewall surfaces of the gate conductors. A second impurity implant, of the same type as the LDD implant but at a higher impurity concentration, is then used to form source/drain ("S/D") implant regions self-aligned with the lateral edges of the gate conductor sidewall spacers. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor turns on.
The semiconductor industry has devoted much effort to reducing the feature sizes of and the separation between adjacent structures, such as conductive interconnects or transistors, in integrated circuits. Reducing the size of structures employed by integrated circuits has resulted in many advantages, including higher circuit speed and increased complexity. This reduction in size, however, and the commensurate increase in density, has also given rise to problems, such as unwanted capacitive coupling between adjacent structures on the integrated circuit device. Applying a voltage across a conductor gives rise to an electric field. As the separation between components of an integrated circuit device decreases, the electric field may cause charge to segregate into an adjacent conductor even in the absence of an applied voltage across the second conductor. Undesirable capacitive coupling may also occur between a gate conductor and an adjacent source/drain region, causing charge to segregate near the source/drain region rather than in the channel region of a transistor. Charge segregation in the absence of an applied voltage may give rise to a false signal (e.g., a logic 1 instead of a logic 0), resulting in improper operation or failure of the integrated circuit device.
An interlevel dielectric is generally deposited across the semiconductor topography following formation of transistors upon and within a semiconductor substrate. The interlevel dielectric is planarized, and contacts are formed through the interlevel dielectric to gate conductors and/or source/drain regions of various transistors. Unfortunately, the relative permittivity of the interlevel dielectric and the gate conductor sidewall spacers somewhat limits the minimum capacitive coupling that can be achieved between gate conductors and adjacent source/drain regions and between adjacent gate conductors. The permittivity .epsilon. of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two layers of a conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. Typically, the permittivity of a material is described as its permittivity normalized to that of a vacuum, .epsilon..sub.0. The relative permittivity, or dielectric constant, .kappa., of a material is therefore defined as EQU .kappa.=.epsilon./.epsilon..sub.0
Silicon dioxide, with a dielectric constant of about 3.7-3.8, is often used as the interlevel dielectric and as the sidewall spacers. Adding fluorine to silicon dioxide or using an organic compound as the dielectric may produce materials with a dielectric constant lower than the dielectric constant of silicon dioxide without fluorine. In some cases, however, this reduction is still insufficient to eliminate capacitive coupling.
It would therefore be desirable to develop a technique for fabricating transistors with reduced capacitive coupling between adjacent gate conductors and between gate conductors and adjacent source/drain regions. An integrated circuit employing those transistors would undergo less charge segregation in undesirable places. As such, the integrated circuit would be more likely to function according to design. Furthermore, feature sizes of the integrated circuit could be reduced without concern over unwanted capacitive coupling. Therefore, reducing lateral capacitive coupling within an integrated circuit would allow for increased integration density of transistors and reduced propagation delay.